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 PD85004
RF power transistor the LdmoST plastic family
Features

Excellent thermal stability Common source configuration Broadband performances POUT = 4 W with 17 dB gain @ 870 MHz Plastic package ESD protection Supplied in tape and reel In compliance with the 2002/95/EC european directive Figure 1. Pin connection
SOT-89
Description
The PD85004 is a common source N-channel, enhancement-mode lateral field-effect RF power transistor. It is designed for high gain, broad band commercial and industrial applications. It operates at 13.6 V in common source mode at frequencies of up to 1 GHz. PD85004's superior gain and efficiency makes it an ideal solution for mobile radio.
Source
Source Gate Drain
Table 1.
Device summary
Marking 8504 Package SOT-89 Packaging Tape and reel
Order code PD85004
August 2008
Rev 2
1/18
www.st.com 18
Contents
PD85004
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ESD protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4 5 6 7 8
Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 RF curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Schematic and BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Demonstration board photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1 8.2 Thermal pad and via design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18
PD85004
Electrical data
1
1.1
Electrical data
Maximum ratings
Table 2.
Symbol V(BR)DSS VGS ID PDISS TJ TSTG
Absolute maximum ratings (TCASE = 25 C)
Parameter Drain-source voltage Gate-source voltage Drain current Power dissipation Max. operating junction temperature Storage temperature Value 40 -0.5 to +15 2 6 150 -65 to +150 Unit V V A W C C
1.2
Thermal data
Table 3.
Symbol RthJC
Thermal data
Parameter Junction - case thermal resistance Value 21 Unit C/W
3/18
Electrical characteristics
PD85004
2
Electrical characteristics
TCASE = +25 oC
2.1
Static
Table 4.
Symbol IDSS IGSS VGS(Q) VDS(ON) CISS COSS CRSS VGS = 0 V VGS = 5 V VDS = 13.6 V VGS = 10 V VGS = 0 V VGS = 0 V VGS = 0 V
Static
Test conditions VDS = 25 V VDS = 0 V ID = 50 mA ID = 0.25 A VDS = 13.6 V VDS = 13.6 V VDS = 13.6 V f = 1 MHz f = 1 MHz f = 1 MHz 3.9 0.27 16 14 1.1 Min Typ Max 1 1 Unit A A V V pF pF pF
2.2
Dynamic
Table 5.
Symbol POUT GPS ND
Dynamic
Test conditions VDD = 13.6 V, IDQ = 50 mA, PIN = 0.1 W, f = 870 MHz VDD = 13.6 V, IDQ = 50 mA, POUT = 4 W, f = 870 MHz VDD = 13.6 V, IDQ = 50 mA, POUT = 4 W, f = 870 MHz Min 4 15 60 20:1 Typ 5 17 65 Max Unit W dB % VSWR
Load VDD = 13.6 V, IDQ = 50 mA, POUT = 4 W, f = 870 MHz mismatch All phase angles
2.3
ESD protection characteristics
Table 6. ESD protection characteristics
Test conditions Human body model Machine model Class 2 M3
2.4
Moisture sensitivity level
Table 7. Moisture sensitivity level
Test methodology J-STD-020B Rating MSL 3
4/18
PD85004
Impedances
3
Impedances
Figure 2. Impedances
Table 8.
Broadband impedances
F(MHz) 860 880 900 920 940 960 ZGS 2.46+ j 6.63 2.59+ j 6.83 2.63+ j 6.97 2.57+ j 7.09 2.42+ j 7.17 2.27+ j 7.34 ZDL 8.38+ j 2,83 8.08+ j 3.46 7.77 + j 4.10 7.50+ j 4.77 7.15+ j 5.37 6.95+ j 6.07
5/18
DC curves
PD85004
4
DC curves
Figure 3. DC output characteristics Figure 4. ID vs VGS
ID vs Vgs
VGS=10V VGS=9V VGS=8V VGS=7V
PD84002
VGS=6V
VGS=5V
VGS=4V
Figure 5.
Capacitances vs drain voltage
30
25 20 15 10 5 0 0 2 4 6
CRSS
COSS
CISS
Capacitance (pF)
8
Vdd (V)
10
12
14
16
6/18
PD85004
RF curves
5
Figure 6.
RF curves
Output power and drain efficiency vs frequency 13.6 V / 50 mA / Pin = 19 dBm
80 70
5
Figure 7.
Gain vs frequency 13.6 V / 50 mA
Gain vs Frequency 13.6V / 50mA
6
20 19 18
60
Pout (W)
4
40 30
Gain (dB)
50
Efficiency (%)
17 16 15 14 13 12 860 Pin=19 dBm
3
Pout
Eff
20 10
2 860
880
900
920
940
0 960
880
900
920
940
960
Frequency (MHz)
Frequency (MHz)
Figure 8.
0 -2 -4 -6
Input return loss vs frequency 13.6 V / 50 mA
13.6V / 50mA
Figure 9.
20 19
Gain vs output power 13.6 V / 50 mA
Pin=19 dBm
18 17
Gain (dB)
IRL (dB)
-8 -10 -12
16 15 14 13
860 MHz 900 MHz 960 MHz
-14 -16 -18 -20 820
12 11 0 1 2 3 4 5 6 7
Pout (W)
840 860 880 900 920 940 960 980 1000
Frequency (MHz)
Figure 10. Drain current vs output power 13.6 V / 50 mA
0.8 0.7
Figure 11. Output power vs input power 13.6 V / 50 mA
40 38
860 MHz
900 MHz
960 MHz
Output power (dBm)
Drain current (A)
36 34 32 30 28 26
860 MHz 900 MHz 960 MHz
0.6 0.5 0.4 0.3 0.2 28 29 30 31 32 33 34 35 36 37 38 39 40
24
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Output Power (dBm)
Input power (dBm)
7/18
RF curves Figure 12. Harmonics vs frequency 13.6 V / 50 mA
0 -10 -20 H2 H3
PD85004
Harmonics (dB)
-30 -40 -50 -60 -70 -80 860
880
900
920
940
960
Frequency (MHz)
8/18
PD85004
Schematic and BOM
6
Schematic and BOM
Figure 13. Schematic
Vcc
1+
MSub
FR4 H=20 mil
R3 B1 B2 C3 C4
+ C5
2-
R2
C1 L1 C2
R1 TL4 TL5 C11 RFin C6 TL1 C8 TL2 C9 TL3 C10 LDMOS PD85004 TL6 C12 C7 RFout
9/18
Schematic and BOM
PD85004
Table 9.
Components part list
Description Ferrite bead Ferrite bead Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Inductor Resistor Potentiometer Resistor 120 pF 1 nF 10 nF 10 uF 39 pF 3.3 pF 12 pF 22 pF 6,8 pF 1,5 pF 12.55 nH 150 10 K 1K 0603 0603 0603 0603 0603 SMT 0603 0603 0603 0603 0603 0603 Value Case size Manufacturer Panasonic Panasonic Murata Murata Murata Panasonic Murata Murata Murata Murata Murata Murata Coilcraft Tyco electronics Bourns electronics Tyco electronics 3214W-1-103E 01623440-1 Part code EXCELDRC35C EXCELDRC35C GRM39-C0G121J50D500 GRM39-X7R102K50C560 GRM39-X7R103K50C560 EEVHB1V100P GRM39-C0G390J50D500 GRM39-C0G3R3C50Z500 GRM39-C0G120J50D500 GRM39-C0G220J50D500 GRM39-C0G6R8D50Z500 GRM39-C0G1R5C50Z500 1606-10
Component ID B1 B2 C1, C2 C3 C4 C5 C6, C7 C8 C9 C10 C11 C12 L1 R1 R2 R3 TL1 TL2 TL3 TL4 TL5 TL6 RF in, RF out PD85004 Board
W= 0.92 mm L = 13.6 mm W=0.92 mm Transmission Line W=0.92 mm W=0.92 mm W=0.92 mm W=0.92 mm SMA-CONN LDMOS 50 L = 3.5 mm L = 4.2 mm L = 3.8 mm L = 4.2 mm L = 11.3 mm 60 mils JOHNSON STMicroelectronics FR-4 THk = 0.020" 2 OZ Cu both sides 142-0701-801 PD85004
10/18
PD85004
Demonstration board photo
7
Demonstration board photo
Figure 14. Demonstration board photo
11/18
Package mechanical data
PD85004
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
12/18
PD85004 Table 10.
Dim. Min A B B1 C C1 D D1 E e e1 H L 1.4 0.44 0.36 0.35 0.35 4.4 1.62 2.29 1.42 2.92 3.94 0.89
Package mechanical data SOT-89 mechanical data
mm. Typ Max 1.6 0.56 0.48 0.44 0.44 4.6 1.83 2.6 1.57 3.07 4.25 1.2 Min 55.1 17.3 14.2 13.8 13.8 173.2 63.8 90.2 55.9 115.0 155.1 35.0 Inch Typ Max 63.0 22.0 18.9 17.3 17.3 181.1 72.0 102.4 61.8 120.9 167.3 47.2
Figure 15. Package dimensions
13/18
Package mechanical data
PD85004
8.1
Thermal pad and via design
Thernal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device. The via pattern is based on thru-hole vias with 0.203 mm to 0.330 mm finished hole size on a 0.5 mm to 1.2 mm grid pattern with 0.025 plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 16. Pad layout details
14/18
PD85004
Package mechanical data
8.2
Soldering profile
Figure 17 shows the recommeded solder for devices that have Pb-free terminal plating and where a Pb-free solder is used. Figure 17. Recommended solder profile
Figure 18 shows the recommeded solder for devices with Pb-free terminal plating used with leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 18. Recommended solder profile for leaded devices
15/18
Package mechanical data Figure 19. Reel information
PD85004
16/18
PD85004
Revision history
9
Revision history
Table 11.
Date 05-Dec-2007 22-Aug-2008
Document revision history
Revision 1 2 Initial release. Updated marking in Table 1 on page 1 Changes
17/18
PD85004
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18/18


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